The invention pertains to phase detectors, and more particularly, to an apparatus and method for increasing the bandwidth and linear operating range of the phase detector.
Phase detectors (also sometimes referred to as phase discriminators) are well known in the art for comparing the phase of two digital signals and converting the phase difference into a DC error voltage. The DC error voltage is typically amplified and used to drive a voltage controlled oscillator in a phase locked loop. Phase locked loops are used in FM demodulation, frequency synthesizing, frequency multiplication, and other applications.
A conventional phase detector 10 is shown in FIG. 1. Phase detector 10 includes three separate and distinct functional blocks: a phase comparator 12, an amplifier 14, and an integrator 16. The phase comparator 12 is shown as a differential NOR gate for providing a digital pulse whose duration is proportional or at least highly correlated with the phase difference between the input waveforms. Therefore, phase comparator 12 receives a first differential input designated A and NA at terminals 20 and 21, and a second differential input designated B and NB at terminals 22 and 23. A differential output pulse designated PI (phase information) and NPI is provided at the output of phase comparator 12. Referring now to FIG. 2, the NOR function of the comparator 12 is shown, wherein PI is at a logic high level if both the A and B inputs are at a logic low level. Phase comparator 12 can also be a single-ended or differential OR gate, exclusive OR gate ("XOR") or exclusive NOR gate ("NXOR"). The XOR and NXOR gates require additional devices to build, but, since they act on both the rising and falling edges of the input signals, supply approximately twice as much energy to the amplifier 14 and integrator 16 for conversion to the DC error signal.
Amplifier 14 is a conventional differential amplifier having a voltage or current controlled output and a predetermined gain for boosting the amplitude of the error pulse from the phase comparator 12. The integrator 16 is a conventional passive integrating circuit including resistors R1, R3, and capacitor C1 coupled to the inverting output terminal 24, and resistors R2, R4, and capacitor C2 coupled to the noninverting output terminal 25. The differential DC output error voltages are designated NPHASE and PHASE. The magnitude of each of the DC error voltages is set by the phase amplifier 14 and the responsiveness of the error voltages is set by the time constants R1C1 and R2C2.
An improved phase detector is shown in U.S. Pat. No. 4,535,459 ("'459") to Charles R. Hogge, Jr. entitled "Signal Detection Apparatus." While the phase detector taught in the '459 patent includes advantages over the prior art phase detector 10 shown in FIG. 1, the phase comparator is separate and distinct from the integrator. Note in FIG. 3 of the '459 patent that XOR gates 46 and 52 drive separate integrator blocks 70 and 74 through an intermediate resistor and capacitor network.
The problem with all such configurations is that the bandwidth of the phase detector is limited by the bandwidth of the phase comparator, approximately equal to one and one half times the propogation delay through the OR/NOR, XOR/XNOR gate used in the phase detector. More precisely, the bandwidth of the gate is a function of the switching speed of the devices used, the gain, and the associated internal and load RC time constants. The dominant poles for the frequency response of the gate are inverse products of the RC time constant and gain, and therefore occur at a significantly lower frequency than the Ft of the devices used in the gate. The error pulse created by the phase comparator is thus filtered by the bandwidth of the comparator. As the phase difference between the inputs approaches 180 degrees or -180 degrees the desired error pulse approaches zero pulse width. Such a pulse is heavily attenuated by a low bandwidth phase comparator and is therefore less useful to provide accurate information proportional to the phase difference between the input signals.
Referring now to FIG. 3, output pulses from a typical bandwidth limited phase comparator are plotted for four phase differences approaching -180 degrees of phase difference. In the uppermost waveform, .phi..sub.3, the phase difference relatively far from -180 degrees, and the pulse required to represent this distance is accurately created by the phase comparator. As the phase difference becomes closer to -180 degrees, the pulse width decreases, but is still capable of being generated as shown in the .phi..sub.2 waveform. As the phase difference further approaches -180 degrees, the output pulse becomes filtered by the bandwidth of the phase comparator, resulting in the "runt" pulse shown in the .phi..sub.1 waveform. The runt pulse does not have the same energy as the desired pulse, and therefore is not proportional to the phase difference of the input signals. Finally, as the phase difference requires a pulse that is almost completely filtered out as shown in the .phi..sub.0 waveform. Any phase differences beyond this point have virtually no effect on the output of the phase comparator.
Referring now to FIG. 4, an ideal plot of phase difference versus phase comparator output pulse width is shown in a solid line. The ideal characteristics for pulse width are a sawtooth waveform in which the pulse width is zero (0% duty cycle) at -180 degrees, and reaches a maximum pulse width (100% duty cycle) at 180 degrees. Ideally, the pulse width is linear between the two phase extremes. The sawtooth pattern repeats for phase differences less than -180 degrees and phase differences greater than 180 degrees. The non-ideal, bandwidth limited response is shown in dashed lines. At small phase differences, the output pulse width is sufficiently large that the effects of the bandwidth are not noticeable, the response lying on the ideal linear curve. However, as the phase difference approaches -180 degrees and 180 degrees, the bandwidth limiting effect appears, and the response becomes essentially flat, providing no information as to the phase difference. The effect at -180 degrees and 180 is usually asymmetrical, further complicating the response of the phase detector.
In operation, a phase locked loop using a bandwidth limited phase comparator will not be able to respond as quickly or over as great a phase difference range as a phase lock loop with an ideal phase comparator. If the input frequency drifts to far from the center frequency (phase difference approaching -180 or 180 degrees), the phase locked loop will lack sufficient gain to "push" the input frequency back to the center frequency.
Therefore, what is desired is a phase detector that does not have the problems associated with the generation and amplification of narrow voltage pulses, is not limited by the bandwidth of the phase comparator, and has a bandwidth as close as possible to the fT of the devices used in the phase detector.